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| TECHNICAL DATA IN74LV273 Octal D Flip-Flop with Common Clock and Reset The IN74LV273 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT273. The IN74LV273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flipflop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. * Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS * Supply voltage range: 1.2 to 5.5 V * Low input current: 1.0 A; 0.1 A at O = 25 N * High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC DIP 20 1 20 1 DW SUFFIX SO ORDERING INFORMATION IN74LV273N IN74LV273DW IZ74LV273 Plastic DIP SOIC chip TA = -40 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM RESET Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 V CC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CLOCK FUNCTION TABLE Inputs Reset L H H PIN 20=VCC PIN 10 = GND H H H= high level L = low level X = don't care Z = high impedance L Clock X D X H L X X Output Q L H L no change no change INTEGRAL 1 IN74LV273 MAXIMUM RATINGS * Symbol VCC IIK * 1 2 Parameter DC supply voltage Input diode current Output diode current Output source or sink current VCC current GND current Power dissipation per package: Plastic DIP * 4 SO * 4 Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds Value -0.5 to +7.0 20 50 25 50 50 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * IO * ICC IGND PD 3 Tstg TL * C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 VI < -0.5 V or VI > VCC + 0.5 V. * 2 VO < -0.5 V or VO > VCC + 0.5 V. * 3 -0.5 V < VO < VCC + 0.5 V. * 4 Derating - Plastic DIP: - 12 mW/C from 70 to 125C SO Package: - 8 mW/C from 70 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, t f DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) 0 V VCC 2.0 V 2.0 V VCC 2.7 V 2.7 V VCC 3.6 V 3.6 V VCC 5.5 V Parameter Min 1.2 0 0 -40 0 0 0 0 Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV273 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol Parameter conditions VCC V 25C min VIH HIGH level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 5.5 5.5 2.7 3.6 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 0.1 8.0 0.2 Guaranteed Limit -40C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 0.1 8.0 0.2 85C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.40 3.60 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.40 0.55 1.0 80 0.5 125C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.50 0.65 1.0 160 0.85 V Unit VIL LOW level output voltage V VOH HIGH level VI = VIH or VIL output IO = -100 A voltage V VI = VIH or VIL IO = -6 mA VI = VIH or VIL IO = -12 mA VOL LOW level VI = VIH or VIL output IO = 100 A voltage V V V VI = VIH or VIL IO = 6 mA VI = VIH or VIL IO = 12 mA II ICC ICC1 Input current Supply current VI = VCC or 0 V VI =VCC or 0 V IO = 0 A V V A A mA Additional VI = VCC - 0.6V supply current per input INTEGRAL 3 IN74LV273 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t r=tf=2.5 ns) Test Symbol Parameter conditions VCC V -40C to 25C min tPHL, tPLH Propagation delay , Clock to Q VI = 0 V or V1 Figures 1,4 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 VI = 0 V or VCC 5.5 max 150 30 22 17 14 160 40 30 23 19 6.0* 40* Guaranteed Limit 85C min max 150 32 24 19 16 160 44 33 26 22 125C min max 150 41 30 24 20 160 56 41 33 28 ns Unit tPHL Propagation delay , Reset to Q VI = 0 V or V1 Figures 2,4 ns CI CPD * T = 25oC Input capacitance Power dissipation capacitance (per flip-flop) pF pF TIMING REQUIREMENTS(CL=50 pF, t r=t f=2.5 ns) Test Symbol Parameter conditions VCC V -40C to 25C min tw Pulse Width, Clock (low or VI = 0 V or V1 high), Reset (low) Figures 1,2,4 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 60 28 21 16 12 40 18 13 11 9 5 5 5 5 5 50 5 5 5 5 max Guaranteed Limit 85C min 70 34 25 20 16 50 22 16 13 11 5 5 5 5 5 50 5 5 5 5 max 125C min 80 41 30 24 20 60 26 19 15 13 5 5 5 5 5 50 5 5 5 5 max ns Unit tsu Setup Time, Data to Clock VI = 0 V or V1 Figures 3,4 ns trem Removal Time, Reset to Clock VI = 0 V or V1 Figures 2,4 ns th Hold Time, Clock to Data VI = 0 V or V1 Figures 3,4 ns INTEGRAL 4 IN74LV273 Clock Frequency fc VI = 0 V or V1 Figures 1,4 1.2 2.0 2.7 3.0 4.5 - 2 17 23 30 32 - 1 14 19 24 27 - 1 12 16 20 24 MHz VOL and VOH are the typical output voltage drop that occur with the output load. Figure 1. Switching Waveforms Figure 2. Switching Waveforms INTEGRAL 5 IN74LV273 Figure 3. Switching Waveforms Symbol VCC V1 VM 1,2 1,2 0,6 2,0 2,0 1,0 Level of a signal, V 2,7 2,7 1,5 TEST POINT 3,0 2,7 1,5 4,5 4,5 2,25 DEVICE UNDER TEST OUTPUT * CL * Includes all probe and jig capacitance Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM INTEGRAL 6 IN74LV273 CHIP PAD DIAGRAM 18 19 1.53 + 0.03 20 17 16 15 14 13 12 11 01 10 02 03 04 05 06 07 Chip marking 25LV273 Y 09 08 (0,0) 1.48 + 0.03 X Location of marking (mm): left lower corner x=0.119, y=0.082. Chip thickness: 0.46 0.02 mm, (0.35 0.02 mm - for SOIC). PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Symbol Reset Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND Clock Q4 D4 D5 Q5 Q6 D6 D7 Q7 VCC Location (left lower corner), mm X 0.1415 0.1415 0.1375 0.4535 0.6245 0.7800 0.9520 1.2685 1.2480 1.2650 1.2650 1.2425 1.2465 0.9520 0.7800 0.6245 0.4535 0.1160 0.1440 0.1190 Y 0.6270 0.3880 0.1515 0.1190 0.1190 0.1190 0.1180 0.1185 0.2960 0.5160 0.8430 1.0820 1.3165 1.3120 1.3110 1.3110 1.3110 1.3115 1.1350 0.9140 Pad size, mm 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 Note: Pad location is given as per passivation layer. INTEGRAL 7 |
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